Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs

We study nand pMOS devices with 3.2–30 nm thick SiON or SiO2 gate dielectrics and n ++ or p doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If holes are provided from the p poly gate and the gate dielectric is sufficiently thin, NBTI-type donor-like defects may occur even under positive bias stress conditions. For devices with sufficiently thick dielectrics or n poly gated devices, holes are absent during PBTI stress and acceptorlike defects are created. 2011 Elsevier Ltd. All rights reserved.